1. Field of the Invention
The disclosure generally relates to a charge pump, and more specifically, to a charge pump for accelerating the locking process and reducing the phase error in a PLL (Phase-Locked Loop).
2. Description of the Related Art
A PLL (Phase-Locked Loop) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circuit consisting of a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal. The phase detector compares the phase of that signal with the phase of the input periodic signal and adjusts the oscillator to keep the phases matched. Bringing the output signal back toward the input signal for comparison is called a feedback loop since the output is “fed back” toward the input forming a loop.
FIG. 1 is a diagram of a conventional PLL 100 with an input node IN and an output node OUT. For example, the PLL 100 may include a phase frequency detector 110, a charge pump 120, a loop filter 130, a VCO (Voltage-Controlled Oscillator) 140, and a frequency divider 150 (optional). When the PLL 100 is locked, the frequency of a reference signal SREF (such as input clock signals) at the input node IN is the same as the frequency of a feedback signal SFB from the output node OUT. The conventional PLL 100 generally has the problem of having either a long locking time or serious jitter and phase error due to the poor design of the charge pump 120. Accordingly, there is a need to design a novel charge pump to overcome the drawbacks of the prior art.